1 Analog view of digital Signals

2 Generalities Interconnects degrade the quality of digital signal  Capacitance: charge and discharge implies reduced edge speed  Inductance: induced voltages implies offsets reducing edges speed, non monotonic edges, delays and logic level violations  Transmission lines: finite propagation speed implies delays and voltage plateaus  Resistance: In short rise/falls times In long interconnects

3 Digital Signal appearance

4 Overshoot/Undershoot: impedance mismatch, crosstalk, ground and power bounce (package), and multiple reflections. Plateaus: usually introduced by long interconnects adding delay depending on where the signal is sampled. monotonic: to prevent double clocking or meta- stability

5 Modeling Frequency contents and Bandwidth Lumped models: small compared with wavelength at the highest interest frequency Digital waveforms split in to categories  Un-terminated: (TTL, CMOS, etc) usually with exponential decay  Terminates: (ECL, LVDS, etc) usually trapezoidal

6 Trapezoidal Systems with small capacitance and terminated nets

8 Exponential Edges Rise and fall depend on  Using the Fourier Transform Excellent with 4/  good with 1/  g Power spectrum, power spectrum envelope Low pass filter requires BW>=1.4/ 

9 Output of a D Flip-Flop

10 Transmission Lines

11 Introduction Any pair of wires and conductors carrying currents in opposite directions form transmission lines. Transmission lines are essential components in any electrical/ communication system. They include coaxial cables, two-wire lines, microstrip lines on printed-circuit-boards (PCB). (Note that at very high frequencies, any conductor on a PCB must be considered as transmission lines.) The characteristics of transmission lines can be studied by the electric and magnetic fields propagating along the line. But in most practical applications, it is easier to study the voltages and currents in the line instead.

12 Examples

13 Fields

14 Wave equation

15 Voltage/Current Waves

16 Voltage and current equations Relation between instantaneous voltage v and current i at any point along the line: For periodic signals, Fourier analysis can be applied and it is more convenient to use phasors of voltage V and current I.

17 Voltage and current equations Decoupling the above equations, we get where is called the propagation constant, and is in general complex. α is the attenuation constant, β is the phase constant.

18 Voltage and current equations The general solutions of the second-order, linear differential equation for V, I are : V+, V-, I+, I- are constants (complex phasors). The terms containing e- γz represent waves travelling in +z direction; terms containing + γz represent waves travelling in –z direction.

19 Lossless transmission line Propagation constant imaginary Equations in time domain Phase Velocity

20 Some transmission lines

21 Careful, approximations grossly wrong for some w,h

22 RG58

23 Transmission lines impedance curves

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26 Driving a line: equivalent circuit

27 Transmission point

28 Termination: Equivalent circuit

29 Reflections and Telegrapher’s equation

30 General transmission line problem

31 Pulse propagation

32 Fast an Slow edges TOF time of flight For slow rise times, the transmitted wave has sufficient time to reflect off the load and return to the driver before the driver has completed its transition. The load then modifies the impedance seen by the driver and affects its switching characteristics. In other words, the driver “feels” the load while it switches. For this situation to occur, the edge rate must be greater than twice the TOF. For fast rise times with edge rates less than twice the TOF, the driver completes its transition before any of the transmitted wave can reflect from the load and return. During the logic transition, the driver sees only the transmission line’s characteristic impedance. In this situation, the loading does not affect the driver’s switching behavior.

33 Source and Parallel Termination  Signaling with fast edges on source terminated and on source plus parallel terminated transmission lines; 1ns rise and fall times with 1ns delay: (a) voltage, (b) power. 2C because of symmetry of vcc and gnd transmission lines

34 Source and Parallel Termination  Signaling with slow edges on source terminated and on source plus parallel terminated transmission lines; 4ns rise and fall times with 1ns delay: (a) voltage, (b) power.

35 Source Termination only Without parallel termination at the load, the +1 reflection coefficient at the load causes the voltage to essentially double. The large reflected wave travels back to the driver where it is absorbed by the matched source impedance. Due to the presence of the reflected waveform, the signal integrity along the transmission line is not good, but it can be quite good at the load, which is where it matters for a point to point net. Unterminated nets are common with both TTL and CMOS to minimize power dissipation. With good source match, the signal integrity at the load can be quite good. However, the reflected wave is signficant and can cause difficulties on more complex topologies (such as multidrop nets). Also, a bidirectional bus using source termination can be slower because it must wait for the signal to return and terminate in the source impedance before the bus can be turned around into receive mode

36 Nonideal Signaling Switching Incidence  If the first incidence is insufficient, then the voltage must build to a sufficient level to trigger the receiver. The voltage wave reflects off of the receiver, propagates back to the source, reflects there, and propagates back to the receiver. If the voltage is sufficient at this second arrival, then the receiver switches, and the signaling is said to be second incidence. If the signal is again insufficient, then switching may occur at the third incidence, fourth incidence, and so on. Anything other than first incidence switching involves a time penalty of two TOFs per incidence.

37 PC Board Test

38 Discontinuities Capacitive Load  The capacitive load introduces a delay adder of τ ln 2. Series inductance  the series inductor causes noise by creating a reflected pulse and adds delay to the signal due to edge rate degradation. For the step input, the reflected pulse voltage peak equals the amplitude of the step, while the delay adder is τ ln 2. For series inductance and shunt capacitance, the frequency-dependent impedance of these discontinuities causes frequency-dependent reflection coefficient

39 Trapezoidal ramp examples

40 Impedance Step The general rule of thumb is to keep all transmission lines at the same characteristic impedance; otherwise, reflections are generated with amplitudes given by the reflection coefficient. impedance of transmission lines can be essentially constant over very broad bandwidths, so the reflection coefficient can be strongly frequency-independent.

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43 Cálculo del largo de pistas velocidad de propagación típica del 66% de la luz:  tr:tiempo de trepada de la señal [ns]  t’pd:tiempo de propagación [ns]  lmax:largo máximo de la pista [cm] Con plano de tierra, utilizando FR-4 se tiene que la longitud máxima aproximada esta dada por:  lmax= 9 x tr  con tiempo de trepadas de 1ns la distancia máxima de una pista es menor a 10 cm

44 Terminaciones de línea:

45 Tipo de terminación Partes agregadas Retardo agregadoConsumoValoresComentario Terminación resistiva en serie 1SíBajoR s = Z 0 - R 0 Buen margen de ruido en continua Terminación resistiva en Paralelo 1PequeñoAltoR= Z 0 El consumo es un problema Red Thevening 2PequeñoAltoR= 2 x Z 0 El consumo en CMOS es un problema Red RC 2PequeñoMedio R= Z 0 C=20~600pF Verificar ancho de banda y capacidad adicionada Red con diodo 2PequeñoBajo- Limita sobre pico; Algo de rebote en los diodos

46 Terminación Serie Ésta alternativa es óptima en los casos donde sólo se tiene una carga al final de la línea, es decir, para enlaces punto a punto. Se utiliza siempre y cuando la impedancia R0 de la fuente sea menor que Z0.Para dimensionar Rs se considera la siguiente condición: Rs  Z0 - R0 Rs: Resistencia serie Z0: Impedancia característica R0: Resistencia de salida de la fuente En la actualidad se suele utilizar una resistencia de 33 . La utilización de la terminación serie minimiza el rebote.

47 Terminaciones al final de la línea Cuando existen varias cargas conectadas a una misma línea o múltiples fuentes están conectadas a una estructura de bus, se utilizan métodos de terminación al final de la línea. La terminación se debe colocar luego del último dispositivo conectado a la línea. Las características de esta técnica de terminación son las siguientes: La señal de interés viaja hacia el final de la línea de transmisión sin degradación en los niveles de tensión y corriente. La tensión transmitida se absorbe en la carga El terminador remueve las reflexiones por ser del mismo valor que la impedancia característica de la línea, amortiguando sobrepicos.

48 Terminación con resistencia en paralelo Esta terminación agrega retardo de propagación al aumentar la constante de tiempo  = R C por el incremento de R en la red.. Una desventaja de la terminación resistiva es el consumo de potencia en continua, dado que se utilizan valores de entre 50  y 150 . En general no se utilizan para familias TTL o CMOS debido a la gran corriente necesaria para mantener los niveles lógicos altos, al utilizar una resistencia a tierra o pull-down. En los casos de lógica ECL la resistencia se conecta a Vcc

49 Terminación Thevening Este tipo de terminación es adecuado tanto para lógicas TTL como CMOS. La resistencia del par RC tiene el valor de la impedancia característica de la línea al igual que en la terminación con resistencia en paralelo. El capacitar frena la tensión continua por lo que la fuente no debe proveer corriente extra debido a la terminación cada vez que se establece un nivel en la línea Desde el punto de vista de la adaptación de impedancias todos los métodos son equivalentes siendo la alternativa RC la que menos potencia consume. La resistencia es del valor de la impedancia característica y el valor de la capacidad es muy pequeño, de entre 20 a 600 pF. La constante de tiempo RC producida por la terminación debe ser dos veces mayor al retardo de propagación de la línea, en general se eligen valores de manera que la constante de tiempo sea tres veces el retardo de propagación de la línea

50 Terminación con diodo Se utilizan diodos principalmente para evitar los sobrepicos con baja disipación de potencia. La principal desventaja es la respuesta a señales de alta frecuencia. Cuando se utilizan diodos rápidos, la velocidad de conmutación de los mismos debe ser de al menos 4 veces el tiempo de trepada de la señal Los diodos no afectan la impedancia por lo que no evitan las reflexiones, por lo que en general si es necesario reducir o compensar la línea debe complementarse con otra técnica de terminación. De todas formas en los casos donde se desconoce la impedancia de la línea es conveniente y sencillo utilizar terminaciones con diodos

51 Crosstalk Leakage of a signal from one conductor to another is called crosstalk, and it can be induced through three coupling mechanisms: capacitive, inductive, and radiative. Radiative coupling is essentially a self-induced EMI disturbance and would be treated within an EMI design framework. This section is concerned with capacitive and inductive coupling.

52 Capacitive Crosstalk A low-to-high transition on the aggressor line produces positive pulses on the victim line, while a high-to-low transition produces negative pulses at the far end, At the near far end,

53 Inductive Crosstalk assuming a triangular edge on the aggressor waveform

54 Total Crosstalk

55 Topology

56 Maximum time rate

57 Eye Diagrams

58 Simultaneous Switching Noise

59 SSN

60 Time Margin

61 Clock Skew

62 Spider leg clock distribution network and and tree distribution

63 Low impedance Clock distribution