1 Introduction to IC DesignTsung-Chu Huang (黃宗柱) Department of Electronic Eng. Chong Chou Institute of Tech. 2003/11/03

2 Outline CMOS Logic Gate Design Standard Cell Layout Gate Array LayoutSea of Gates CMOS Layout Guideline Transmission Gate Layout MUX Layout CMOS Logic Structures Clocking Strategies I/O Structures Low-Power Design

3 To that nearest to output in the serial transistorsFan-In and Fan-Out A D Fanin=3 Fanout=4 A D To that nearest to output in the serial transistors

4 CMOS Gate Stage-Ratio Principle(Review) IO PAD

5 Transistor Stage-Ratio Principle1 ↓ CDS OCg s:1 Rp/s rOCg output part internal part

6 Transistor Stage-Ratio Principle Equal Rise/Fall Time DesignNormalized-mobility

7 Transistor Stage-Ratio Principle High-Speed Design GuidelineUse NAND instead of NOR gates Place inverters at high-fanout nodes Fanin < 5; Fanout < 10 Use min.-sized gates on high-fanout nodes; Keep Rise/Fall edges sharp

8 Complex Logic Gate LayoutEuler Path (Review)

9 CMOS(互補金氧半) Logic P型網路為F(X)的Relay logic N型網路為F(X)的Relay logic P型網路 F XAND與OR互換即可 N型網路為F(X)的Relay logic

10 Stick Diagram 常用佈局表示法及簡化佈局法 例： 格子(Grid)狀文字(Font)表示法EDIF 為一種(層次，對角座標)的表示法 Stick diagram: 草圖用，將不重要寬度省略 例： 2/0.35 1/0.35

11 例如：F=(A+B)(C+D) A B C D A B C D 因為F= A B + C D P型網路為： 因為F=(A+B)(C+D) AN型網路為：

12 尤拉路徑 (Euler Path) 十八世紀拓樸學被用來簡化CMOS邏輯閘佈局 N型路徑為N型Relay-logic網路P型路徑為P型Relay-logic網路 拓樸學證明各輸入開關X與X交叉通過！ B A F S F D

13 尤拉路徑 (Euler Path)佈局法 再畫出兩倍寬度的P+IMP 先畫出一倍寬度的N+IMP A B VDD B A F S D A BVSS

14 Interlaces of Diffusion LinesB C D E A B C E D Vdd Out Vss Out A B E D C A B E D C

15 Minimum Interlace AlgorithmExample: A B C D E F Out Out Vss F E D C A B Out Vdd

16 Minimum Interlace AlgorithmAdding a pseudo input to each sub-gate such that each sub-gate has odd inputs. A B C D E F 2 interlaces

17 Minimum Interlace AlgorithmRotate each axis to reduce the inner interlaces A B C D E F

18 Output Capacitance MinimizationB C D COA COBCD COBCD >> COA Put Output-point here because

19 Stacking along Diffusion LinesExample: considering a buffer with a stage ratio of 2 Area: A2 1:2 Area: A1 Ln1+Ln2 Wn1+Wn2 Area: A3 Vinv↗

20 Channel Routing I H A B B C C A D F D To reduce #Tracks E G I B A G F

21 LEA: Left-Edge AlgorithmSort by length Select from Left Edge A B C D F G E Length Edge

22 Rapid Prototyping Prototyping: Q< Rapid Prototyping: t(Q) << t(Qproduct) Usual Rapid Prototyping wrt. Full Custom Semi-Custom: saving the prior processes Weinberger Array, Gate Array, SOG, e.t.c. Standard-Cell: saving PLD SPLD CPLD FPGA

23 Weinberger Array (NOR Logic)D E F G

24 Gate Matrix

25 Gate Array

26 SOG: Sea-of-Gates

27 Physical Layout SkillsWidening methods: Crossover:

28 Physical Layout SkillsDog-bone/Dog-Leg: No need to change layers for crossing More usage of white space: Rubber forcing

29 Folding Lines of DiffusionExample: Full Adder

30 Folding Lines of DiffusionExample: Full Adder A B C Co Co Sum

31 Folding Lines of DiffusionExample: Sum=A⊕B⊕C A B B A C C A B F Y V F Y V S X F S X F

32 Connections of Standard Cells1. Butting 1. Wired 3. Feedthrough

33 Transmission Gate Layout Consideration

34 Multiplex A B C Z 1 A B C A B

35 Multiplex Layout A B

36 Pass-Transistor and Transmission GateHigh-Z or Vth-Degrade PASS Transistor Logic Circuit Pull-up or Pull-down PASS Transistor Logic Circuit A B

37 Address Decoder using Pass Transistor

38 4-Transistor XOR and XNORB Bui et al. New 4-Transistor XOR and XNOR Designs, AP-ASIC2000.

39 Scope & Review on the MidtermLectures from 9/22~11/3. Stick diagram, inv(ENM, ERF, Stage) Multiple choice on common guidelines SPICE Netlist and 3 Major Analyses