1 MMIC Design Flow Anurag Nigam
2 NatTel Microsystems Pvt. Ltd.Tutorial 2 Bias Decoupling or Matching Output Matching Input Matching Active Device 1 2 3 Day1 NatTel Microsystems Pvt. Ltd.
3 Six Caps of a MMIC DesignerMMIC stands for ‘Monolithic Microwave Integrated Circuit’. Due to high frequency, dimensions of lumped components are comparable to wavelength. This makes lumped components behave like distributed circuits. Substrate coupling, package & board parasitic dominate and affect the response of MMIC. Package Design & EM Simulations Thermal Design & Modeling Layout & EM Simulations Circuit Design Sensitivity, Yield & DOE Design Spins & Documentation RF Testing Board Designs & Assembly NatTel Microsystems Pvt. Ltd.
4 NatTel Microsystems Pvt. Ltd.On Chip MMIC Circuits Power Amplifier (PA) Low Noise Amplifier (LNA) T/R Switch (SPDT) Circulator Patch Antenna Array Patch Antenna Power Limiter Voltage Controlled Oscillator (VCO) Mixer Band Pass Filter (BPF) High Pass Filter (HPF) Low Pass Filter (LPF) Band Stop Filter (BSF) Power Combiner/ Divider Hybrid Digital Attenuator Digital Phase Shifter NatTel Microsystems Pvt. Ltd.
5 NatTel Microsystems Pvt. Ltd.Typical Gain Block Bias Decoupling or Matching Output Matching Input Matching Active Device Bypass Cap At DC, Bypass Capacitors are open. At RF, ideally, Bypass Capacitors are short . Role of this capacitor is to isolate Device Impedance from output impedance of DC Supply Voltage. Coupling Cap Role of Coupling Capacitor is to couple Device and Source/Load Impedance at RF and isolate DC from Load and Source Impedance. This capacitor can be small and part of high pass matching circuit. Device Impedance With inductive load Bias Decoupling or Matching Bias De-coupling circuit impedance appears in parallel to device impedances. Ideally they should be open circuit at frequency of interest so as to provide full Smith Chart Impedance Range. Th demerit is narrow band width of the circuit and stability issues at high frequency. Instead of Bias Decoupling, an inductor can be used as part of matching. The merit of using low value inductor is low DC drop across it resulting is higher -1dB Gain Compression Point of Circuit and better stability at High Frequency. Demerit of using an Inductor is lower Impedance Range (Excursion to edge of Smith Chart is not possible, not suitable for large transistors with small impedances) Input/output Matching Matches Device Impedance to 50Ω. Lossless network is bilateral Active Device Active device provides RF Gain. NatTel Microsystems Pvt. Ltd.
6 Typical Absorptive Type Switch1 2 3 Bypass Cap Coupling Cap Roles of Coupling Capacitor & Bypass Capacitor are explained earlier. Bias Decoupling Resistance is used for decoupling as the gate does not draw any current. Bypass Capacitor and decoupling resistance present impedance to gate that decides phase of S21 across the pass transistors T1 and T3. Pass Transistors When On, Pass Transistors decide Insertion Loss of the switch. Insertion loss of switch in On path decides Power Capability of Transmit Chain and Noise Figure of Receive Chain. When Off, Drain to Source Capacitance of Pass Transistors decides Off Path Isolation. Operation in brief For Port 1 to be connected to Port 2, T1 and T2 are On and T3 and T4 are Off. Bypass Transistors When On, Bypass Transistors terminate the off port in 50Ω. When Off, Drain to Source Capacitance of Bypass Transistors decides on port impedance and hence the insertion loss of On Path. NatTel Microsystems Pvt. Ltd.
7 Gallium Arsenide (GaAs) Process1 GHz 2 GHz 5 GHz 10 GHz 20 GHz 50 GHz 100 GHz HP 07 Power MESFET (0.7um) PPH 25 Power PHEMT (0.25um) PPH 25x High Power PHEMT (0.25um) PPH 15 Power PHEMT (0.15um) PH 25 Low Noise PHEMT (0.25um) PH 15 Very Low Noise PHEMT (0.15um) HB20P R/O High Power /Oscillator InGaP HBT HB20L Low Cost InGaP HBT HB20S Very High Power L-S Band InGaP HBT BES 100 Schottky Diode Technology Process we will explore through our designs 4” GaAs Wafer Various UMS GaAs Processes NatTel Microsystems Pvt. Ltd.
8 NatTel Microsystems Pvt. Ltd.UMS PH 15 Process Summary NatTel Microsystems Pvt. Ltd.
9 NatTel Microsystems Pvt. Ltd.Layout Design Rules Cell Names should not conflict Only capital are acceptable in cell names Maximum of 16 characters are acceptable in cell names ‘A’-’Z’, ‘0’-’9’ and ‘_’ are only acceptable characters in cell names Maximum vertices acceptable in a polygon is 200 All polygons should have enclosed areas. Lines, poly-lines and curves are not acceptable Hierarchical Layout is acceptable (No need to flatten p-cells) At Wafer Level all dimensions should be multiples of 1um Coincident patterns and cells including GR and PL Layers are not acceptable Transistor Gate Widths should be along horizontal direction Angles should be multiple of 45° or 90° except for patterns in EL Layers Chip dimensions should be multiple of 10 um Chip aspect ratio should be less than 3 Minimum distance between any pattern and dicing street is 20 um Minimum distance between Substrate Via edge and dicing street is 55 um Minimum dimensions of bond pad are 100 um x 100 um Minimum distance between bond pads is 50 um Text is written in CO Layer using DRC free UMS Alphabets Dicing streets should be continuous across the wafer 6 mm x 6.1 mm < tile size< 14 mm x 14 mm Substrate Via in straight lines are not acceptable Tile y dimension should not be in range 7 to 7.45 mm, 9 to 9.58 mm, 12.6 to 13.4 mm Area has to be reserved for PCM Cell Minimum distance between bond pad and air bridge is 50 um Minimum distance between MIM Capacitor and bond pad is 50 um NatTel Microsystems Pvt. Ltd.
10 UMS PH 15 Process- Substrate ViaEL DPC TR N1 CO GaAs 30 x 30 80 x 80 First Step in design at microwave frequency is to determine Substrate Via Inductance First Effort to setup EM Simulation is ADS is to define Metal Stack We have to inspect other components to have complete idea of Substrate Definition in ADS NatTel Microsystems Pvt. Ltd.
11 NatTel Microsystems Pvt. Ltd.MIM Capacitor air-bridge (PEL) DPC EL N1 Dimensions of top electrode Dimensions of bottom electrode Dimensions of the bridge NatTel Microsystems Pvt. Ltd.
12 NatTel Microsystems Pvt. Ltd.Air Bridge EL PEL Silicon Nitride Passivation With Boron Implant Gold Plated Metal (EL) Air TiPtAu Metal (N1) Silicon Nitride (MIM) GaAs Gold Plated Metal (TR) NatTel Microsystems Pvt. Ltd.
13 Approximate Substrate Definition in ADSBoundary: Open, Er -Real: 1, Loss Tangent: 0 FreeSpace PEL Bridge EL N1 GaAs Cond MIM_SiN Pass_SiN Model: Thick (up), thickness: 3.3um, Real: 5.8e7S/m Thickness: 2 um, Er -Real: 1, Loss Tangent: 0 EL_VAB Model: Thick (up), thickness: 3.3um, Real: 5.8e7S/m T: 0.19 um, Er -Real: 7.2, TanD: DPC Model: Thick (up), thickness: 0.5um, Real: 3.4e7S/m T: 0.2 um, Er -Real: 7.2, TanD: DPC_VIA CO Model: Thick (up), thickness: 0.19um, Real: 0.125e7S/m Thickness: 100 um, Er -Real: 12.8, Loss Tangent: EL_DUMMY Model: Thick (down), thickness: 2.69mil, Real: 4.1e7S/m FreeSpace2 Boundary: Open, Er -Real: 1, Loss Tangent: 0 DPC_VIA, DPC Model: 2D Distributed, Real: 3.4e7S/m EL_VAB Model: 3D Distributed, Real: 3.4e7S/m EL_DUMMY Model: 3D Distributed, Real: 4.1e7S/m NatTel Microsystems Pvt. Ltd.
14 NatTel Microsystems Pvt. Ltd.Microstrip Lines EL GaAs Cond T W L NatTel Microsystems Pvt. Ltd.
15 NatTel Microsystems Pvt. Ltd.TaN Resistance NatTel Microsystems Pvt. Ltd.
16 NatTel Microsystems Pvt. Ltd.TiWSi Resistance NatTel Microsystems Pvt. Ltd.
17 GaAs Resistance- SiN with BoronNatTel Microsystems Pvt. Ltd.
18 NatTel Microsystems Pvt. Ltd.Inductors Fixed inner radius n=20 um air-bridges Input node Output node Fixed 26 um x 26 um Fixed Spacing s=5um Variable Width W=5, 10, 15, 20 um EL N1 NatTel Microsystems Pvt. Ltd.
19 Maximum Current RatingsLayer Component Max. DC current Max. RF Power Imax1(Mean) Imax2(RMS) EL Line, inductor, bridge 7.5 mA/ um 47 mA/ um GR/PL FET gate - 3 mA/ um 3mA/ um RM TaN resistor 0.4 mA/ um 5 uW/ um sqr. 0.45 mA/ um 1 mA/ um RHRW TiWSi resistor 0.1 mA/ um 10 uW/ um sqr. 0.2 mA/ um N1 Inductor, interconnection 2 mA/ um 22 mA/ um ZAL GaAs resistor 0.8 ma/ um 77 uW/ um sqr. 0.8 mA/ um NatTel Microsystems Pvt. Ltd.
20 NatTel Microsystems Pvt. Ltd.Dicing Street Rules NatTel Microsystems Pvt. Ltd.
21 PHEMT Device Models NatTel Microsystems Pvt. Ltd. GaAs InGaAs AlGaAsOhmic metal (CO) T-shaped Al Gate Silicon Nitride Passivation TiPtAu (N1 Metal) Silicon Nitride Dielectric Gold Plated Metal (EL) Linear Model for Low Noise Amplifier Design Non-Linear Cold Model for Switching Circuits Non-Linear Hot Model for Power Circuits NatTel Microsystems Pvt. Ltd.
22 NatTel Microsystems Pvt. Ltd.Maximum DC Ratings NatTel Microsystems Pvt. Ltd.
23 Technological process step NatTel Microsystems Pvt. Ltd.Layout Guidelines Layer Name GDSII Num. Technological process step Min. Grid ZAL 02 Boron Isolation 0.1 um CO 03 Ohmic Contacts PL 41 Gate Bus 0.005 um GR1 14 Gate (0.15 um) GR2 44 Gate (other dimension) OUV 38 Nitride Opening on CO RHRW 16 TiWSi resistor RM 06 TaN resistor RMG 17 Al/ Au diffusion barrier layer N1 04 MIM bottom electrode DPC 05 Nitride Opening PEL 39 Air-bridge Layer EL 40 Gold Plating Metal TR 10 Via-hole DCFA 11 Backside Dicing Street The recommended grid size for layout is 1 um. Sub-micron grid is acceptable in cells. Spacing, Width, Overlapping, Overhanging, and Enclosure rules for various layers should be read prior to attempting layout and layout based designs NatTel Microsystems Pvt. Ltd.