1 VHDL Application Workshopmodule Relational_Operators (A,B,Y1,Y2,Y3,Y4); input[2:0] A,B; output Y1,Y2,Y3,Y4; (Aor B) begin Y1 = A< B; Y2 = A <= B; Y3 = A > B; if ( A>= B ) Y4 =1; else Y4 = 0; end endmodule October 11,12 and 13, 1999 Lecturer : Mr.Watcharakon Noothong Tel : (662) Ext 611 ณ. ศูนย์ฝึกอบรมการออกแบบวงจรรวม ชั้นที่ 21 อาคารมหานครยิปซั่ม ถนนศรีอยุธยา พญาไท กรุงเทพฯ
2 Couse Outline Day 1 1. Introduction and Overview- H/W Description Language - History, Limitation - Design flow 2. Introduction to VHDL - VHDL language Abstraction - VHDL Components 3. Data types and Object Declarations - Scalars and Array Literals - Name (Identifiers) - Object Declarations Day 2 4. VHDL Operators - Logical Operators - Relational Operators - Concatenation Operator - Arithmatic Operator 5. Sequential Statements - Process Statement - Variable assignment Statement - Functions and Procedure 6. Concurrent Statements - Concurrent signal assignments - Condition signal assignments - Selected signal assignments - BLOCK Statement Day 3 7. Advanced Topics - Extend types - Composite types - Overloading - RTL Styles 8. Testbench - Different levels of testbench - Waveform generators - TextIO 9. VHDL & Logic Synthesis - Adder, Comparator - Multiplexor, Decoder - Registers ,Counter
3 What is VHDL ? VHSIC (Very High Speed Integrated Circuit) Hardware Description Language
4 VHDL History Department of Defense (DoD) developed in 1981IEEE Standrad (VHDL’87) IEEE Standrad (VHDL’93)
5 VHDL Limitation
6 Hardware Description Language (HDL)The VHDL is a software programming language used to model the intended operation of a piece of hardware, similar to Verilog-HDL. Use of the VHDL Language 1. Documentation Language: To provide human and machine readable documentation 2. Design Language: To provide a structure reflecting hardware design and hierarchy and provide methods to handle complexity by partitioning the design. 3. Verification Language: To provide a concurrent method verifying hardware interaction and provide constructs for stimulating a design. 4. Test Language: To provide ability to generate test vectors, multiple testbench strategies and method to write self checking code. 5. Synthesis Language: To provide high-level constructs that can be translated to boolean equations and then translate them to gate as well as to provide constructs that can be optimized.
7 System Design SpecificationElectronic System Design System Design Specification Hardware/Software Co-Design Hardware Design Specification Software Design Specification ASIC Boards and Systems FPGA PLD Std Parts
8 Top-Down Design MethodologyThe top-level system is modeled for functionality and performance using a high-level behavioral description. Each major component is modeled at the behavioral level and the design is simulated again for functionality and performance. Each major component is modeled at the gate level and the design is simulated again for timing, functionality and performance.
9 Behavioral level of abstraction pyramid
10 VHDL language abstractionsinputs Function outputs Behavioral Hardware system specification Standard parts models Dff RTL ASIC/FPGA design for synthesis Synthesizable models Logic Gate level design PLD design Layout Full custom design
11 VHDL Components Aim and Topics Introduction to : Entity design unitArchitecture design unit Package design unit Configuration design unit
12 Introduction VHDL design consists of several separate four design units : Entity design unit Architecture design unit Configuration design unit Package design unit component VHDL Compiler Entity architecture configuration package Entity architecture configuration package Design Units Library
13 Architecture declarationComponent VHDL Component entity HALFADD is port ( A, B : in bit; SUM, CARRY : out bit ); end HALFADD; Entity declaration architecture BEHAVE of HALFADD is begin SUM <= A xor B; CARRY <= A and B; end BEHAVE; Architecture declaration
14 Entity declaration Syntax: entity entity_name is generic (generic_list); port( port_name :
15 Entity declaration exampleentity MUX is port ( IN0, IN1, SEL : in bit; OUTPUT : out bit ); end entity MUX; IN0 IN1 OUTPUT SEL VHDL 93 entity MUX is generic( TPLH : time:= 3 ns; TPHL : time:= 5 ns ); port ( IN0, IN1, SEL : in bit; OUTPUT : out bit ); end MUX; IN0 IN1 OUTPUT SEL tplh tphl
16 Architecture Design UnitStructural or beheviorual description Decribes an implementation of an entity Must be associated with a specific entity Single entity can have many architectures
17 Architecture DeclarationSyntax: architecture architecture_name of entity_name is declarations begin concurrent_statements end architecture_name; VHDL 93 ! Can now optionally include the reserved word architecture after the reserved word end in the entity declaration
18 Architecture styles Algorithmic description BehavioralRegister Transfer Level (RTL) Dataflow Netlist representation Structural Behavioral, Dataflow, Structural Mixed-Level
19 Behavioral style architecturearchitecture BEHAVIORAL of MUX is begin process (IN0, IN1, SEL) begin if (SEL = ‘0’) then OUTPUT <= IN0; else OUTPUT <= IN1; end if; end process; end BEHAVIORAL;
20 output = (sel . in0) + (sel. in1)Dataflow style architecture architecture DATAFLOW of MUX is begin OUTPUT <= ( (not SEL) and IN0) or (SEL and IN1); end DATAFLOW; output = (sel . in0) + (sel. in1)
21 Structural style architecturearchitecture STRUCTURAL of MUX is component INV port (I1 : in bit; O1 : out bit ); end component; component AND2 port (I1, I2 : in bit; O1 : out bit ); component OR2 signal INT0, INT1, INT2 : bit; begin G0 : INV : port map ( I1 => SEL, O1 => INT0); G1 : AND2 : port map ( I1 => IN0, I2 => INT0, O1 => INT1); G2 : AND2 : port map ( I1 => SEL, I2 => IN1, O1 => INT2); G3 : OR2: port map ( I1 => INT1, I2 => INT2, O1 => OUTPUT); end STRUCTURAL;
22 Packages Design Unit Package declaration Package BodySubprogram declarations Type declarations Component declarations Deferred constant declaration Package Body Subprogram body Defered constant value
23 Packages declaration Syntax: package package_name is[exported_subprogram_declarations] [exported_constant_declarations] [exported_components] [exported_type_declarations] [attribut_declarations] [attribut_specifications] end package_name; package body package_name is [internal_subprogram_declarations] [internal_subprogram_bodies] [internal_type_declarations]
24 Packages declaration examplepackage MY_PACKAGE is type MY_TYPE1 is ... type MY_TYPE2 is ... function MY_MEAN (A, B, C: real) return real; procedure MY_PROC1 ( …); … end MY_PACKAGE; package body MY_PACKAGE is function MY_MEAN (A, B, C : real) return real is begin return(A + B + C)/ 3; end MY_MEAN; ...
25 Configuration Design UnitSelect a particular architecture of an entity from library
26 Configuration declarationSyntax: configuration configuration_name of entity_name is for architecture_name end configuration_name ;
27 Configuration Exampleconfiguration CFG_HALFADD of HALFADD is for STRUCTURAL end for; end CFG_HALFADD; Selection of entities and architectures Select architecture of top level entity Select entity/architecture pairs for component instances Consider as “parts list” for hierarchy Default configuration If names of entities & components match Last analysed architecture of enties Non-default configuration Map specifiec entities, architectures
28 Design Hierarchy entity FULLADD is port (A, B, CIN : in bit;SUM, CARRY : out bit ); end FULLADD; architecture STRUC of HALFADD is signal N_SUM N_CARRY1, N_CARRY2 : bit; - - other declarations begin U1 : HALFADD port map (A, B, N_SUM, N_CARRY1); U2 : HALFADD port map (N_SUM, CIN, SUM, N_CARRY2); U3 : ORGATE port map (N_CARRY2, N_CARRY1, CARRY); end STRUCl;
29 Signals and Datatypes Aim and Topics Introduction to : Type conceptStandard types Scalar and Array Literal IEEE Standard Logic Object declaration Constant declaration Signal declaration Varable declaration
30 Concept of a Type Type must be defined when signal is declaredEither in Port section of an entity Architecture, in a signal declaration Types must match up !
31 Standard Data Types package STANDARD is type boolean is (FALSE, TURE);type bit is (‘0’ , ‘1’); type character is (- - asc ii set ); type integer is range type real is range - - bit_vector, string, time end STANDARD;
32 Standrad Data Types Provided within VHDLType Range of values Examples declaration integer -2,147,483,647 to +2,147,483,647 signal index : integer := 0; real E +38 to +1.0E variable val : real := 1.0; boolean (TURE, FALSE) variable test : boolean := TRUE; character defined in package STANDRAD variable term : character := bit 0, 1 signal in1 : bit := ‘0’; bit_vector array with each element of the type variable pc : bit_vector(31 downto 0); time fs, ps, ns, us, ms, sec, min, hr variable delay : time := 25 ns; string array with each element of type character variable name : string(1 to 4) := “tmec”; natural 0 to the maximum integer value in the variable index : natural := 0; implementation positive 1 to the maximum integer value in the variable index : natural := 0;
33 Scalars and Array LiteralsScalar Type Array Type character string bit bit_vector std_logic std_logic_vector boolean real integer time
34 The Problem With Type BitOnly has values ‘1’ and ‘0’ Defualt initialisation to ‘0’ Simulation and synthesis require other values Unknown High impedance Don’t care Different signal strengths
35 MVL Systems Problum with type BIT : use of Multi-Valued Logic System (MVL) Enumerated type defining unknown, high-impedance, etc Until early 1992, no standard Standard now set Nine state system defined and agreed by IEEE Standard IEEE 1164
36 IEEE Standard Logic In package “ Std_Logic_1164”“std_logic” has same values as “std_ulogic” std_logic std_logic_vector std_ulogic std_ulogic_vector
37 Rules for Using Std_Logic and Std_Ulogic
38 Object Declarations Aim and Topics Introduction to :Constant declaration Signal declaration Variable declaration
39 Constant Declaration Constant is name assigned to a fixed valueSyntax : constant constant_name : type := value; Constant is name assigned to a fixed value You need only change the constant declaration in one place Constant makes a design more readable and makes updating code easy Example constant Vdd : real := ; constant CYCLE : time := 100 ns ; constant PI : real := 3.14 ; constant FIVE : bit_vector := “0101” ; constant TEMP : std_logic_vector(8 to 11) := “0101” ;
40 Signal Declaration Syntax : Examplesignal signal_name : type ; OR signal signal_name : type := initial_value; Signal connect design entities together and communicate changes in values between processes. Signal can be abstractions of physical wires, busses, or used to document wires in an actural circuit. Signal with a type must be declared before the signal is used. Example signal A_BUS, A_BUS, Z_BUS : bit_vector (3 downto 0); signal A_BIT, B_BIT, C_BIT, D_BIT : bit; signal BYTE : bit_vector (7 downto 0); signal COUNT : integer range 1 to 50; signal GROUND: bit := ‘0’; signal SYS_BUS : std_bit_vector (31 downto 0);
41 Signal Assigment Signal of same type Language definesbit_vector (array of bit) string (array of character) Define size when declaring signal/port
42 Signals and Drivers Signal value changed with “Signal Assignment Statement” Signal driver Types must match Resolved signal
43 Alias Declaration Syntax : alias alias_name : alias_type is object_name; An alias is an alternative name for an existing object (signal, variable or constant) It dose not define a new object Example signal COUNT : bit_vector(7 downto 0); alias SIGN_BIT : bit is COUNT(7); alias LSB_BIT : bit is COUNT(0); alias NIBBLE_L : bit_vector(3 downto 0) is COUNT(3 downto 0); alias NIBBLE_H : bit_vector(3 downto 0) is COUNT(7 downto 4);
44 Variable Declaration Syntax : variable variable_name : type; OR variable variable_name : type := initial_value; Variable is a name assigned to a changing value within a process Variable assignment occurs immediately in simulation Variable can be used as a temporary simulation value Variable must be declared before it is used Example variable INDEX : integer range 1 to 50; variable MEMORY : bit_vector(0 to 7); variable X, Y : integer ; variable CYCLE_TIME : TIME range 10 ns to 50 ns := 10 ns;
45 VHDL Operators Aim and Topics Introduction to : Logical OperatorsRelational Operators Concatenation Operator Arithmatic Operator
46 Logical Operators and, or, nand, nor, xor (equal precedence)not (higher precedence) Pre-defined for bit bit_vector std_ulogic, std_logic std_ulogic_vector, std_logic_vector xnor VHDL 93 ! Shift operators : sll (shift left logical), srl (shift right logical), sla (shift left arithmetic) , sra (shift right arithmatic), rol (rotate left logical), ror (rotate right logical)
47 Logical Operators : Examplesentity AND2 is port ( A_BIT, B_BIT : in bit; Z_BIT : out bit ); end AND2; architecture RTL of AND2 is begin Z_BIT <= A_BIT and B_BIT; end RTL;
48 Logical Operators on ArraysOperands same length and type Operations on matching elements signal A_BUS, B_BUS, Z_BUS : std_logic_vector (3 downto 0); Z_BUS <= A_BUS and B_BUS; Equivalent to Z_BUS(3) <= A_BUS(3) and B_BUS(3); Z_BUS(2) <= A_BUS(2) and B_BUS(2); Z_BUS(1) <= A_BUS(1) and B_BUS(1); Z_BUS(0) <= A_BUS(0) and B_BUS(0);
49 Relational Operators Result is boolean ( TRUE or FALSE)Often used with if - then - else
50 Relational Operations : RulesOperands must be of the same type Arrays May be of different lengths Aligned left and compared Can lead to unusual result ! No numerical meaning
51 BYTE <= A_BUS & B_BUS ;Concatenation Operator Ampersand ( & ) means concatenation in VHDL signal Z_BUS : bit_vector ( 3 downto 0 ) ; signal A, B, C, D : bit ; signal BYTE : bit_vector ( 7 downto 0 ) ; signal A_BUS : bit_vector ( 3 downto 0 ) ; signal B_BUS : bit_vector ( 3 downto 0 ) ; Z_BUS <= A & B & C & D ; concatenation BYTE <= A_BUS & B_BUS ;
52 Arithmetic Operators Predefined for Not defined forinteger real (except mod and rem) Physical types ( e.g. time) Not defined for bit_vector std_ulogic_vector std_logic_vector Generally, operands must be of the same type
53 Adder example + a b z entity ADDER isport ( A, B : in integer range 0 to 7 ; Z : out integer range 0 to 15 ) ; end ADDER; architecture ARITHMETIC of ADDER is begin Z <= A + B ; end ARITHMETIC; a b + z
54 Arithmetic of Time Testbenches, cell delays Multiplication / divisionMultiply / divide by integer /real returns type time
55 Concurrent and Sequential StatmentsAim and Topics To introduce some of the most commonly used concurrent and sequential statements The process statement Sequential statements If the else Case For loop Concurrent forms of if and case Condition signal assignment Selected signal assignment
56 Process Statement Syntax :optional_label: process (optional_sensitivity_list) subprogram_declarations type_declarations constant_declarations variable_declarations other_declarations begin sequential_statements end process optional_label;
57 Sequential statementsProcess Statement example label Sensitivity list MUX : process (A, B, SEL) begin if (SEL = ‘1’) then Z <= A; else Z <= B; end if; end process MUX; Sequential statements
58 Processes within VHDL Codearchitecture A of E is begin - - concurrent statements P1 : process - - sequential statements end proccess P1; P2 : process end proccess P2; end A; P1 : process begin - - sequential statements end proccess P1; P2 : process begin - - sequential statements end proccess P2;
59 IF Statement Syntax : Example if condition then sequential_statements. . . end if; Example if (A = ‘1’) then COUNT := COUNT + 1 ; end if;
60 IF-Else Statement Syntax : Example if condition thensequential_statements . . . else end if; Example if (A = ‘1’) then COUNT := COUNT + 1 ; else COUNT := COUNT - 1 ; end if;
61 IF-ELSIF Statement Syntax : Example if condition_1 thensequential_statements elsif condition_2 then else sequenctial_statements end if; Example if (A = ‘1’) then COUNT := COUNT + 1 ; elsif (A= ‘0’) then COUNT := COUNT - 1 ; else COUNT := COUNT * 1 ; end if;
62 IF Example Library IEEE; use IEEE.Std_Logic_1164.all;entity IF_EXAMPLE is port ( A, B, C, D : in std_logic_vector ( 3 downto 0 ); SEL : in std_logic_vector ( 1 downto 0 ); Z : out std_logic_vector ( 3 downto 0 ) ); end IF_EXAMPLE; architecture IF_STATE of IF_EXAMPLE is begin process (A, B, C, D, SEL) if (SEL = “00”) then Z <= A ; elsif (SEL = “01”) then Z <= B ; elsif (SEL = “10”) then Z <= C ; else Z <= D ; end if; end process; end IF_STATE;
63 CASE Statement No choices may overlap All choices must be specifiedSyntax : case expression is when choice => sequential_statements ; . . . end case; Example case SEL is when “00” => Z <= A ; when “01” => Z <= B ; when “10” => Z <= C ; when OTHERS => Z <= D ; end case ; No choices may overlap All choices must be specified specifically or with “others”
64 Defining Ranges Beware !Library IEEE; use IEEE.Std_Logic_1164.all; entity CASE_EXAMPLE is port ( A, B, C, SEL : in integer range 0 to 15 ; Z : out integer range 0 to 15 ); end CASE_EXAMPLE; architecture CASE_STATE of CASE_EXAMPLE is begin process (A, B, C, SEL) case SEL is when 0 to 4 => Z <= B ; when 5 => Z <= C ; when OTHERS => Z <= A ; end process; end CASE_STATE; Beware ! Array do not have a discrete sequence of values associated with them case SEL is when “11” => when “00” to “10” => when OTHERS =>
65 Loop Statement Avaiable in a process Label is optionalFor Loop Statement While Loop Statement Label is optional Use range attributes ‘high ‘low ‘range For loop identifier not declared Can’t be altered not visible outside loop Synthesis Style For loop synthesisable for fixed range. While generally not synthesiseable.
66 For Loop Statement Iterated around a loopSyntax : optional_label:for parameter in range loop sequential_statements end loop optional_loop; Example LOOP1 : for INDEX in 0 to 7 loop DOUT(INDEX) <= DIN(INDEX); end loop LOOP1; Iterated around a loop Loop variable gets values in the range No need to declare loop variable It is illegal to make an assignment to the loop variable
67 For Loop Example Library IEEE; use IEEE.Std_Logic_1164.all;entity EX is port ( A, B, C : in std_logic_vector( 4 downto 0 ); Q : out std_logic_vector( 4 downto 0 ) ); end EX; architecture FOR_LOOP of EX is begin process (A, B, C) for I in 0 to 4 loop if A(I) = ‘1’ then Q(I) <= B(I); else Q(I) <= C(I); end if; end loop; end process; end;
68 While Loop Statement Available in a processSyntax : optional_label: while condition loop sequential_statements end loop optional_label; Example Available in a process Not generally synthesiseable Useful in testbenches Reading from file . . . Generation of clock for specific time P1 : process (A) variable INDEX : integer := 0 ; begin LOOP1 : while INDEX < 8 loop DOUT(INDEX) <= DIN(INDEX); INDEX := INDEX + 1 ; end loop LOOP1; end process P1;
69 The Wait Statement Suspends execution of processExecution continues when statement satisfied Four formats . . . Wait for : wait for specific_time; A specific time wait on signal_list; An event on signals (equivalent to a sensitivity list) wait until condition; A condition to occur (requires event) wait; Indefinitely (never to be reactivated)
70 Wait Examples Library IEEE; use IEEE.Std_Logic_1164.all;entity D_FLOP is port ( D, CLK : in std_ulogic; Q : out std_ulogic ); end D_FLOP; architecture A of D_FLOP is begin process wait until CLK’event and CLK = ‘1’; Q <= D; end process; end A; STIMULUS : process begin SEL <= ‘0’ ; BUS_B <= “0000”; BUS_A <= “1111”; wait for 10 ns; SEL <= ‘1’ ; - - ETC, ETC end process STIMULUS; No sensitivity list
71 Variables Declared within process Assignment immediatelysignal A, B, C, Y, Z : integer; begin P1 : process (A, B, C) variable M, N : integer ; M := A; N := B; Z <= M + N; M := C; Y <= M + N; end process P1; Declared within process Assignment immediately Like “software” Only be used within process Called its “scope” Retains value Assigns : signal to variable variable to signal
72 Variables Versus Signalssignal A, B, C, Y, Z : integer; begin P1 : process (A, B, C) variable M, N : integer ; M := A; N := B; Z <= M + N; M := C; Y <= M + N; end process P1; signal A, B, C, Y, Z : integer; signal M, N : integer; begin P1 : process (A, B, C, M, N) M <= A; N <= B; Z <= M + N; M <= C; Y <= M + N; end process P1;
73 Variables Usage Model Variables used for algorithmsAssign signals to variables Perform algorithm Assign variables to signals Variable cannot be accessed outside of its process
74 Subprograms There are two sorts of subprogramFunctions One return value Procedures Zero or more retrun values Subprogram can be defined in three places in the VHDL code : Package Architecture Process
75 Function declaration Syntax :function function_name (parameter_list) return type is types, constants, other functions, other declarations begin sequential_statements . . . end function_name; entity is end . . . architecture of is begin process end process; end ; Function Declaration Function Calls
76 Function Examples Parameter listfunction PARITY_FUNC ( X : std_ulogic_vector ) return std_ulogic is variable TMP : std_ulogic ; begin TMP := ‘0’ ; for J in X’range loop TMP := TMP xor X(J); end loop; return TMP; end PARITY_FUNC; Function name Returned value
77 Function Call function PARITY_FUNC ( X : std_ulogic_vector )return std_ulogic is variable TMP : std_ulogic ; begin TMP := ‘0’ ; for J in X’range loop TMP := TMP xor X(J); end loop; return TMP; end PARITY_FUNC; 8 DATA_BYTE PARITY_BYTE 16 DATA_WORD PARITY_WORD entity PARITY is port ( DATA_BYTE : in std_ulogic_vector(7 downto 0); DATA_WORD : in std_ulogic_vector(15 downto 0); PARITY_BYTE : out std_ulogic; PARITY_WORD : out std_ulogic ); end PARITY; architecture FUNC of PARITY is - - function declaration begin PARITY_BYTE <= PARITY_FUNC(DATA_BYTE); PARITY_WORD <= PARITY_FUNC(DATA_WORD); end FUNC; Actual parameter
78 Procedure DeclarationSyntax : procedure procedure_name (parameter_list) is types, constants, other functions, other declarations begin sequential_statements . . . end procedure_name; entity is end . . . architecture of is begin process end process; end ; Procedure Declaration Procedure Calls
79 Procedure Examples Parameter list Procedure nameprocedure PARITY_PROC ( X : std_ulogic_vector; signal PARITY_BIT : out std_ulogic) is variable TMP : std_ulogic; begin TMP := ‘0’; for J in X’range loop TMP := TMP xor X(J); end loop; PARITY_BIT <= TMP; end PARITY_PROC; Assignment to “out” parameters
80 Procedure Call procedure PARITY_PROC ( X : std_ulogic_vector;signal PARITY_BIT : out std_ulogic) is variable TMP : std_ulogic; begin TMP := ‘0’; for J in X’range loop TMP := TMP xor X(J); end loop; PARITY_BIT <= TMP; end PARITY_PROC; 8 DATA_BYTE PARITY_BYTE 16 DATA_WORD PARITY_WORD entity PARITY is port ( DATA_BYTE : in std_ulogic_vector(7 downto 0); DATA_WORD : in std_ulogic_vector(15 downto 0); PARITY_BYTE : out std_ulogic; PARITY_WORD : out std_ulogic ); end PARITY; architecture PROC of PARITY is - - procedure declaration begin PARITY_PROC(DATA_BYTE, PARITY_BYTE); PARITY_PROC(DATA_WORD, PARITY_WORD); end PROC; Actual paramenter
81 Defining Subprograms Package Architecture Processarchitecture FUNCTIONS of PARITY is function PARITY_FUNC ( X : std_ulogic_vector) return std_ulogic is variable TMP : std_ulogic; begin TMP : = ‘0’ ; for J in X’range loop TMP := TMP xor X(J); end loop; return TMP; end PARITY_FUNC; PARITY_BYTE <= PARITY_FUNC(DATA_BYTE); PARITY_WORD <= PARITY_FUNC(DATA_WORD); end FUNCTIONS; Package Architecture Process package P_FUNCS is function PARITY_FUNC( x : std_ulogic_vector) return std_ulogic ; end P_FUNCS; package body P_FUNCS is function PARITY_FUNC(x : std_ulogic_vector) return std_ulogic; variable TMP : std_ulogic; begin TMP : = ‘0’ ; for J in X’range loop TMP := TMP xor X(J); end loop; return TMP; end PARITY_FUNC;
82 Concurrent StatementsAim and Topics To introduce some of the most commonly used concurrent Concurrent signal assignment Condition signal assignment Selected signal assignment BLOCK statement
83 Concurrent Assignment StatementsX <= A + B; Z <= C + X; Z <= C + X; X <= A + B; Concurrent Order independent What you write is what you get . . . A X + B + Z C
84 Don’t Create Feedback Loops !Y X <= X + Y; + X
85 Concurrent Versus Sequentialarchitecture A of E is begin - - concurrent statements P1 : process - - sequential statements end proccess P1; P2 : process end proccess P2; end A; P1 : process begin - - sequential statements end proccess P1; P2 : process begin - - sequential statements end proccess P2;
86 Concurrent Signal AssignmentsConcurrent Form architecture FORM_1 of V_VAR is begin OUTPUT_Q <= DATA_IN; end V_VAR; Sequential Form architecture FORM_1 of V_VAR is begin process (DATA_IN) OUTPUT_Q <= DATA_IN; end process; end V_VAR;
87 Multiple Concurrent AssignmentsSignals are “wired together” VHDL requires a resolution function Z <= A + B; Z <= C + D; A + B Z ? C + D
88 Multiple Assignments in a Processarchitecture CONCURRENT of MULTIPLE is signal A, B, C, D : std_ulogic; signal Z : std_logic; begin Z <= A and B; Z <= C and D; end CONCURRENT; architecture SEQUENTIAL of MULTIPLER is signal Z, A, B, C, D : std_ulogic; begin process (A, B, C, D) Z <= A and B; Z <= C and D; end process; end SEQUENTIAL; A + C B Z ? + Z C + D D
89 Multiple Assignments : Exampleprocess (A, B, SEL) begin if (SEL = ‘1’) then Z <= A; else Z <= B; end if; end process; process (A, B, SEL) begin Z <= B; if (SEL = ‘1’) then Z <= A; end if; end process; Last assignment takes effect After process suspends Code is equivalent
90 Conditional Signal Assignmententity BRANCH is port ( A, B, C, X : in integer range 0 to 7 ; Z : out integer range 0 to 0 ); end BRANCH; Concurrent version of “ If ” Only one target Must have an unconditional else architecture USE_IF of BRANCH is begin process (A, B, C, X) if (X > 5) then Z <= A; elsif (X < 5) then Z <= B; else Z <= C; end if; end process; end USE_IF; architecture USE_WHEN of BRANCH is begin Z <= A when X > 5 else B when X < 5 else C ; end USE_WHEN ;
91 Selected Signal Assignmententity BRANCH is port ( A, B, C, X : in integer range 0 to 7 ; Z : out integer range 0 to 0 ); end BRANCH; Concurrent version of “case” Only one target Rule as for case architecture USE_IF of BRANCH is begin process (A, B, C, X) case X is when 0 to 4 => Z <= B; when 5 => Z <= C; when OTHERS => Z <= A; end case; end process; end USE_IF; architecture USE_WITH of BRANCH is begin with X select Z <= B when 0 to 4 , C when 5 , A when OTHERS; end USE_WITH;
92 Block/Guarded StatementConcurrent statement Without a guard condition a block is a grouping together of concurrent statements within an architecture Syntax : label: block (optional_guard_condition) declarations begin concurrent_statements . . . end block label; Example Level-Sensitive Latch B1 : block (ENB = ‘1’) begin DOUT <= guarded DIN; end block B1; Edge-Sensitive Flip-Flop B2 : block (CLK’event and CLK = ‘1’) begin DOUT <= guarded DIN; end block B2;
93 Advanced Types Aim and Topics Enumerated types SubtypesComposite types Arrays Array of array Record
94 Enumerated Type DefinitionsVHDL allows the user to define his own type “Enumerated Type” Types cannot be intermixed ! Beware ! Sythesis tools usually offer a way tp map each enumeration to a bit pattern
95 Z_BUS <= ( A_BIT, B_BIT, C_BIT, D_BIT );Aggregates signal A_BUS, A_BUS, Z_BUS : bit_vector (3 downto 0); signal A_BIT, B_BIT, C_BIT, D_BIT : bit; signal BYTE : bit_vector (7 downto 0); Z_BUS <= ( A_BIT, B_BIT, C_BIT, D_BIT ); aggregates BYTE <= ( 7 => ‘1’, 5 downto 1 => ‘1’, 6 => B_BIT, OTHERS => ‘0’ ); Beware ! Some low cost synthesis tools may not support aggregates
96 Subtype declaration Syntax : Examplesubtype subtype_name is base_type range range_constraint; Example type WORD is array (31 downto 0) of bit; subtype NIBBLE is WORD range 3 downto 0; subtype BYTE is WORD range 7 downto 0; subtype MY_BUS is WORD range 15 downto 0;
97 Equivalent statementsArray type declaration Syntax : type type_name is array (array_range) of array_type; Example type WORD8 is array (1 to 8) of bit; type WORD8 is array (integer range 1 to 8) of bit; type BYTE is array (7 downto 0) of bit; type WORD is array (31 downto 0) of bit; type MEMORY is array (0 to 4095) of word; type T_CLOCK_TIME is array (3 downto 0) of integer; Equivalent statements
98 Arrays Assignments Z_BUS <= C_BUS; Beware !signal Z_BUS : bit_vector (3 downto 0); signal C_BUS : bit_vector (0 to 3); Z_BUS <= C_BUS; Z_BUS (3) < C_BUS (0) Z_BUS (2) < C_BUS (1) Z_BUS (1) < C_BUS (2) Z_BUS (0) < C_BUS (3) Beware ! Size of arrary on left and right must be equal Elements are assigned by postion, not element number
99 Slice of an Arrays Beware !signal Z_BUS, ABUS : bit_vector (3 downto 0); signal B_BIT : bit; signal BYTE : bit_vector (7 downto 0); BYTE(5 downto 2) <= A_BUS; Z_BUS(1 downto 0) <= ‘0’ & B_BIT; B_BIT <= A_BUS (0); Z_BUS <= C_BUS; Beware ! The slice direction must be the same as the signal declaration BYTE(5 downto 2) <= A_BUS; Z_BUS(0 to 1) <= ‘0’ & B_BIT;
100 Multi-Dimensional Arraystype MEMORY is array ( 0 to 7, 0 to 3) of bit; constant ROM : MEMORY := ( (‘0’, ‘0’, ‘0’, ‘0’), (‘0’, ‘0’, ‘0’, ‘1’), (‘0’, ‘0’, ‘1’, ‘0’), (‘0’, ‘0’, ‘1’, ‘1’), (‘0’, ‘1’, ‘0’, ‘0’), (‘0’, ‘1’, ‘0’, ‘1’), (‘0’, ‘1’, ‘1’, ‘0’), (‘0’, ‘1’, ‘1’, ‘1’) ); Example Reference : DATA_BIT := ROM(5, 3);
101 Array of Arrays type WORD is array ( 0 to 3 ) of bit;type MEMORY is array (0 to 4) of WORD; variable ADDR, INDEX : integer; variable DATA : WORD; constant ROM : MEMORY := ( (‘0’, ‘0’, ‘0’, ‘0’), (‘0’, ‘0’, ‘0’, ‘1’), (‘0’, ‘0’, ‘1’, ‘0’), (‘0’, ‘0’, ‘1’, ‘1’), (‘0’, ‘1’, ‘1’, ‘1’) ); DATA := ROM(addr) ; ROM(ADDR) (INDEX) To access a single bit
102 Records declaration b7 b6 b5 b4 b3 b2 b1 b0 type T_PACKAGE is recordaddress b7 b6 b5 b4 b3 b2 b1 b0 Parity (ODD) data nibble A ‘1’ (high byte) type T_PACKAGE is record BYTE_ID : bit; PARITY : bit; ADDRESS : integer range 0 to 3; DATA : bit_vector (3 downto 0 ); end record; signal TX_DATA, RX_DATA : T_PACKAGE; . . . RX_DATA <= TX_DATA; TX_DATA <= ( ‘1’, ‘0’, 2, “0101”); TX_DATA.ADDRESS <= 3; Refernce name record
103 Advanced Topics Aim and Topics Overloading Definition RTL CodeSynthesis Coding Styles
104 Overloading Re-define operators Different data types Called in context
105 Subprogram Overloadingpackage P_SUBP is function SINE (L : integer) return real; function SINE (L : real) return real; function SINE (L : std_logic_vector) return real; use work. P_SUBP.all; entity OVERLOADED is port ( A_BUS : in std_ulogic_vector (3 downto 0); B_INT : in integer range 0 to 15; C_REAL : in real; A, B, C : out real ); end OVERLOADED; architecture A of OVERLOADED is begin A <= SINE(A_BUS); B <= SINE(B_INT); C <= SINE(C_REAL); end A; Function 3 Function 1 Function 2 Any subprogram can be overloaded
106 Argument Overloading package P_AVERAGE isfunction AVERAGE (A, B : integer) return integer; function AVERAGE (A, B, C : integer) return integer; function AVERAGE (A, B, C, D : integer) return integer; end P_AVERAGE ; use work. P_AVERAGE.all; entity OVERLOADED is port ( A1, A1, C1 : in integer; V1, V2, V3 : out integer ); end OVERLOADED; architecture ARG_OVER of OVERLOADED is begin V1 <= AVERAGE(A1, B1, C1); V2 <= AVERAGE(A1, C1); V3 <= AVERAGE(A1, B1, C1, D1); end ARG_OVER; Function 2 Function 1 Function 3 arguments
107 Operator Overloading package P_ARITHMETIC isfunction “+” (L: std_ulogic_vector; R: std_ulogic_vector) return integer; function “+” (L: std_ulogic_vector; R: std_ulogic_vector) return std_ulogic_vector; function “+” (L: std_ulogic_vector; R: integer) return std_ulogic_vector; function “+” (L: integer; R: std_ulogic_vector) return std_ulogic_vector; use work.P_ARITHMETIC.all; entity OVERLOADED is port ( A_BUS, B_BUS : in std_ulogic_vector (3 downto 0); A_INT, B_INT : in integer range 0 to 15; Y_BUS, Z_BUS : out std_ulogic_vector (3 downto 0); Y_INT, Z_INT : out integer range 0 to 15 ); end OVERLOADED; architecture A of OVERLOADED is begin Y_INT <= A_INT + B_INT; Z_INT <= A_BUS + B_BUS; Z_BUS <= A_BUS + B_BUS; Y_BUS <= A_BUS + A_INT; Z_BUS <= A_BUS + B_INT; end A; Function 1 Function 2 Function 3 Function 4
108 RTL (Register Transfer Level) Style
109 Complete Sensitivity ListsList all signals read Synthesis : complete for combinational logic process (A, B, SEL) begin if (SEL = ‘1’) then Z <= A; else Z <= B; end if; end process;
110 Incomplete AssignmentsLibrary IEEE; use IEEE.Std_Logic_1164.all; entity INCOMP_IF is port ( EN, D : in std_ulogic; Q : out std_ulogic ); architecture A of INCOMP_IF is begin process (EN, D) if (EN = ‘1’) then Q <= D; end if; end process; end A; What is the value of Q if EN = ‘0’ ? What hardware should be built if this is synthesised?
111 What is the value of Q if EN = ‘0’ ?Rules for Synthesis of Combinational Logic Complete sensitivity list Default assignments to prevent latches Sensitivity list process (A, B, SEL) begin if (SEL = ‘1’) then Z <= A; else Z <= B; end if; end process; process (EN, D) begin if (EN = ‘1’) then Q <= D; end if; end process; What is the value of Q if EN = ‘0’ ?
112 “Ideal” Design Flow Ideally do RTL and gate simulation in same simulator Historical issues Library standrad Slow simulation
113 Describing a Rising Clock for Synthesisprocess begin wait until CLK’event and CLK = ‘1’ and CLK’last_value = ‘0’ ; Q <= D; end process; process begin wait until CLK= ‘1’; Q <= D; end process; process begin wait until CLK’event and CLK = ‘1’; Q <= D; end process; process (CLK) begin if (CLK = ‘1’) then Q <= D; end if; end process; process (CLK) begin if (CLK’event and CLK = ‘1’) then Q <= D; end if; end process;
114 Register Inference in SynthesisLibrary IEEE; use IEEE.Std_logic_1164.all; entity COUNTER is port ( CLK : in std_ulogic; Q : out integer range 0 to 15 ); end COUNTER; architecture A of COUNTER is signal COUNT : integer range 0 to 15 ; begin process (CLK) if CLK’event and CLK = ‘1’ then if (COUNT >= 9) then COUNT <= 0; else COUNT <= COUNT + 1; end if; end process; Q <= COUNT end A; Registers are infered on all signal assignments in clocked processes
115 Asynchronous Reset RegistersLibrary IEEE; use IEEE.Std_logic_1164.all; entity ASYNC_FLOP is port ( D, CLK, RST : in std_ulogic; Q : out std_ulogic ); end ASYNC_FLOP; architecture B of ASYNC_FLOP is begin process (CLK, RST) if (RST = ‘1’) then Q <= ‘0’; elsif (CLK’event and CLK = ‘1’) then Q <= D; end if; end process; end B; If / Elsif structure final elsif has edge no else Has a sensitivity list !!
116 Clocked Process Rules Wait form If formprocess (CLK, RST) begin if (RST = ‘1’) then - - reset all registers elsif (CLK’event and CLK = ‘1’) then - - all combination logic end if; end process; Wait form No sensitivity list If form clock and reset only in sensitivity list All signals assigned get a register process (CLK) begin if (CLK’event and CLK = ‘1’) then - - all combination logic end if; end process;
117 Design Organisation and ManagementAim and Topics Design units Name spaces Elaboration, initialisation, the simulation cycle Compilation order Naming and managing files Effective use of packages within design teams Design partitioning across files
118 Testbench Coding StylesAim and Topics Testbench configurations Stimulus styles Assertions
119 Testbench OrganisationSimple testbench Just send data to design No interation Few processes Sophisticated testbench Models environment around design Talks to design Evolves towards boards model Stimulus Design to verify Testbench (environment) Design to verify
120 Stimulus from Loops Library IEEE; use IEEE.Std_logic_1164.all;entity TESTBENCH is end TESTBENCH; architecture USE_LOOP of TESTBENCH is signal A_BUS : std_ulogic_vector (7 downto 0); begin process for I in 0 to 4 loop A_BUS <= To_Std_ulogic( I, A_BUS’length); wait for 10 ns; end loop; end process; end USE_LOOP;
121 Stimulus from Array Constantarchitecture USE_ARRAY of TESTBENCH is signal A_BUS : std_ulogic_vector (7 downto 0); type T_DATA is array (0 to 4) of std_ulogic_vector(7 downto 0); constant DATA : T_DATA := ( “ ”, “ ”, “ ”, “ ”, “ ” ); begin process for I in DATA’range loop A_BUS <= DATA(I); wait for 10 ns; end loop; end process; end USE_ARRAY;
122 “In line” Stimulus architecture IN_LINE of TESTBENCH issignal A_BUS : std_ulogic_vector (7 downto 0); begin process A_BUS <= “ ”; wait for 10 ns; A_BUS <= “ ”; - - ETC, ETC end process; end IN_LINE;
123 Print if condition is falseAssertions Syntax : assert condition report string_expression severity severity_level; Severity levels defined in package STANDARD NOTE WARNING ERROR (default) FAILURE (usually causes simulation to halt) architecture BEHAVE of TESTBENCH is signal RESULT : bit; . . . begin process constant EXPECTED : bit := ‘1’; assert RESULT = EXPECTED report “Unexperted result !” severity ERROR; wait; end process; end BEHAVE; Print if condition is false
124 Creating Clock and Resetssignal CLK : std_logic := ‘0’; constant PERIOD : time := 50 ns; CLK <= not CLK after PERIOD/2; RESET <= ‘1’ , ‘0’ after 3 * PERIOD; constant INITIAL_CLOCK : std_logic := ‘1’; constant MAX_CYCLES : integer := 1000 ; constant SIM_END_TIME : time := PERIOD * MAX_CYCLES; process begin while NOW <= SIM_END_TIME loop CLK <= INITIAL_CLOCK; wait for PERIOD/2; CLK <= not INITIAL_CLOCK; end loop; assert FALSE report “ Simulation is Over !”; severity FAILURE; end process;
125 Stimulus from a File E.g. image data Created by another program/toolTestbench (environment) Design to verify E.g. image data Created by another program/tool
126 Reading from a File use Std.TextIO.all;architecture READFILE of TESTBENCH is signal A_INT, B_INT : integer; begin process variable L : line; stroes a complete line from file variable INT : integer; reference to specific file file TEXT_FILE : text is in “stimulus.vec”; while not endfile(TEXT_FILE) loop readline(TEXT_FILE, L); read a complete line into VECTOR read(L, INT); read the first integer into INT A_INT <= INT; read(L, INT); read the second integer into INT B_INT <= INT; wait for 10 ns; end loop; end process; end READFILE; 23 21 32 1 45 54 stimulus.vec
127 TextIO Capabilities Able to read/write Procedures used for file IO:bit, bit_vector boolean character, string integer, real time Procedures used for file IO: read(. . .) readline(. . .) write(. . .) writeline(. . .) Reference LRM section 14.3 Testbench (environment) Design to verify
128 TextIO Advantages Stimulus easy changing Less analysis/compile timeTestbench (environment) Design to verify Stimulus easy changing Less analysis/compile time
129 Use of Subprograms Testbench is behavioural Gets large quicklyprocedure MEM_WRITE (DATA: in T_DATA; ADDr: in T_ADDR) is begin - - Memory write procedure end MEM_WRITE; porcedure MEM_READ (DATA: out T_DATA; ADDr: in T_ADDR) is end MEM_READ; procedure MEM_INIT( ) is begin MEM_WRITE(“1000”, “00”); MEM_WRITE(“0100”, “01”); MEM_WRITE(“0010”, “10”); MEM_WRITE(“0001”, “11”); end MEM_INIT; Testbench is behavioural Gets large quickly Use software style structure Function and procedures procedure MEM_TEST( ) is variable VALUE_READ : T_DATA; begin MEM_INIT( ); MEM_READ (VALUE_READ, “01”); if VALUE_READ /= “0100” then . . . end MEM_TEST;
130 Output from SimulationTestbench (environment) Design to verify input Errors Warnings Visualisation Result for comparison Result for analysis Manufacturing test vectors
131 Output from SimulationTestbench (environment) Design to verify input Can output to Simulator output (assertion) File (textIO) Best to keep errors and warnings separate Errors : have to fix these ! Warnings : help to debug issues Errors Warnings
132 Visualised Output Testbench Design to verify input Visualised Output(environment) Design to verify input Visualised Output
133 Results for Comparion Compare results for different simulationsEssential for large designs Studying waveforms very tedious ! If comparing gbetween abstraction levels (Behavioural/RTL, RTL/Gates) Output sequence of data values Time independent Testbench (environment) Design to verify input Compare (diff) Visualised Output Known good results
134 Results for Analysis When simulation goes wrongMore detail than results for comparison Do not mix results for comparison with results for analysis Testbench (environment) Design to verify input Results for analysis
135 Manufacturing Test VectorsMay use simulation output for part/all of manufacturing test Strobe values when they will be stable in gate level design Testbench (environment) Design to verify input Manufacturing test vectors
136 Logic Synthesis with VHDLAim and Topics Combinational circuit Synthesis Multiplexors Encoder & Decoder Comparators Sequential circuit Synthesis Latch D-type Flip-Flop Synchonous Flip-Flop Asynchonous Flip-Flop
137 Basic Design MethodologyRequirements RTL Model Simulate Synthesize Gate-level Model Simulate Test Bench ASIC or FPGA Place & Route Timing Model Simulate
138 2 to 1 Multiplexor Synthesized Circuit Library IEEE;use IEEE.Std_logic_1164.all; entity MUX_2_1 is port ( A, B : in std_logic; SEL : in std_logic; Q : out std_logic ); end MUX_2_1; architecture B of MUX_2_1 is begin Q <= A when (SEL = '0') else B; end B; Synthesized Circuit
139 4 to 1 Multiplexor Synthesized Circuit Library IEEE;use IEEE.Std_logic_1164.all; entity MUX_4_1 is port( A, B, C, D : in std_ulogic_vector(3 downto 0); SEL : in std_ulogic_vector(1 downto 0); Q : out std_ulogic_vector(3 downto 0) ); end MUX_4_1; architecture B of MUX_4_1 is begin process(A, B, C, D, SEL) if (SEL = "00") then Q <= A; elsif (SEL = "01") then Q <= B; elsif (SEL = "10") then Q <= C; else Q <= D; end if; end process; end B; Synthesized Circuit
140 8 to 3 Encoder Synthesized Circuit library IEEE;use IEEE.Std_Logic_1164.all; entity ENCODE_8_3 is port(A : in std_ulogic_vector(7 downto 0); Q : out std_ulogic_vector(2 downto 0) ); end ENCODE_8_3; architecture BEHAVE of ENCODE_8_3 is begin P1: process(A) case A is when " " => Q <= "000"; when " " => Q <= "001"; when " " => Q <= "010"; when " " => Q <= "011"; when " " => Q <= "100"; when " " => Q <= "101"; when " " => Q <= "110"; when " " => Q <= "111"; when others => Q <= "XXX"; end case; end process P1; end BEHAVE; Q <= "000" when A = " " else "001" when A = " " else "010" when A = " " else "011" when A = " " else "100" when A = " " else "101" when A = " " else "110" when A = " " else "111" when A = " " else "XXX";
141 3 to 8 Decoder Synthesized Circuit use IEEE.Std_Logic_1164.all;entity DECODE_8_3 is port(A : in std_ulogic_vector(2 downto 0); Q : out std_ulogic_vector(7 downto 0) ); end DECODE_8_3; architecture BEHAVE of DECODE_8_3 is begin P1: process(A) case A is when "000" => Q <= " "; when "001" => Q <= " "; when "010" => Q <= " "; when "011" => Q <= " "; when "100" => Q <= " "; when "101" => Q <= " "; when "110" => Q <= " "; when others => Q <= " "; end case; end process P1; end BEHAVE;
142 Tri-State buffers Synthesized Circuit library IEEE;use IEEE.Std_Logic_1164.all; entity TRI_STATE is port(A : in std_ulogic_vector(7 downto 0); EN : in std_ulogic; Q : out std_ulogic_vector(7 downto 0) ); end TRI_STATE; architecture RTL of TRI_STATE is begin process(A, EN) if (EN = '1') then Q <= A; else Q <= "ZZZZZZZZ"; end if; end process; end RTL;
143 Bidirectional BuffersLibrary IEEE; use IEEE.Std_Logic_1164.all; entity INOUT_EX is port(IO1, IO2 : inout std_ulogic; CTRL : in std_ulogic); end INOUT_EX; architecture RTL of INOUT_EX is signal OUTBUF, INBUF : std_ulogic; begin IO1 <= IO2 when (CTRL = '1') else 'Z'; IO2 <= IO1 when (CTRL = '0') else 'Z'; end RTL; Synthesized Circuit
144 4-Bit Arithmetic Logic Unit (ALU)ALU4BIT Q <= A and B Q <= A or B Q <= A xor B Q <= A + B Q begin process(A,B,CIN,MODE) variable vsum: std_logic_vector(3 downto 0); variable cy: std_logic; case MODE is when MODE_AND => Q <= A and B; COUT <= '-'; when MODE_OR => Q <= A or B; when MODE_XOR => Q <= A xor B; when others => -- generate 4-bit adder cy := cin; for i in 0 to 3 loop vsum(i) := (A(i) xor B(i)) xor cy; cy := (A(i) and B(i)) or (cy and (A(i) or B(i))); end loop; Q <= vsum; COUT <= cy; end case; end process; end BEHAVE; B COUT MODE CIN Library IEEE; Use IEEE.Std_logic_1164.all; entity ALU4BIT is port( A, B : in std_logic_vector(3 downto 0); MODE : in std_logic_vector(1 downto 0); CIN : in std_logic; Q : out std_logic_vector(3 downto 0); COUT : out std_logic ); end ALU4BIT; architecture BEHAVE of ALU4BIT is constant MODE_AND: std_logic_vector(1 downto 0) := "00"; constant MODE_OR: std_logic_vector(1 downto 0) := "01"; constant MODE_XOR: std_logic_vector(1 downto 0) := "10"; constant MODE_ADD: std_logic_vector(1 downto 0) := "11";
145 Synthesized Circuit
146 Finite State Machine library ieee; use ieee.std_logic_1164.all;entity state_ex is port (in1, clock, reset : in std_logic; out1 : out std_logic_vector (1 downto 0)); end state_ex; architecture state_ex_a of state_ex is signal cur_state, next_state : std_logic_vector (1 downto 0); begin process (clock, reset) if clock = '1' and clock'event then if reset = '0' then cur_state <= "00"; else cur_state <= next_state; end if; end process; process (in1, cur_state) begin case cur_state is when "00" => if in1 = '0' then next_state <= "10"; out1 <= "00"; else next_state <= "01"; out1 <= "10"; end if; when "01" => next_state <= cur_state; out1 <= "01"; when "10" => next_state <= "11"; when "11" => next_state <= "00"; when others => null; end case; end process; end state_ex_a;
147 Synthesized Circuit
148 D-Latchs Synthesized Circuit Level-Sensitive library IEEE;use IEEE.Std_Logic_1164.all; entity LATCH_4BIT is port (D : in std_logic_vector(3 downto 0); EN : in std_logic; Q : out std_logic_vector(3 downto 0) ); end LATCH_4BIT; architecture BEHAVE of LATCH_4BIT is begin P1: process(D, EN) if (EN = '1') then Q <= D; end if; end process P1; end BEHAVE; B1 : block (EN = ‘1’) begin Q <= guarded D; end block ; Level-Sensitive
149 Asynchronous Reset Flip-FlopLibrary IEEE; use IEEE.Std_logic_1164.all; entity ASYNC_FLOP is port ( D, CLK, RST : in std_ulogic; Q : out std_ulogic ); end ASYNC_FLOP; architecture B of ASYNC_FLOP is begin process (CLK, RST) if (RST = ‘1’) then Q <= ‘0’; elsif (CLK’event and CLK = ‘1’) then Q <= D; end if; end process; end B; Synthesized Circuit Edge-Sensitive
150 Synchronous Reset Flip-FlopLibrary IEEE; use IEEE.Std_logic_1164.all; entity SYNC_FLOP is port ( D, CLK, RST : in std_ulogic; Q : out std_ulogic ); end SYNC_FLOP; architecture B of SYNC_FLOP is begin process wait until (CLK’event and CLK = ‘1’); if (RST = ‘1’) then Q <= ‘0’; else Q <= D; end if; end process; end B; Synthesized Circuit Edge-Sensitive
151 Ripple Carry Adder Carry Lookahead Adder
152 Adder (Look Ahead)
153 Adder (Ripple Carry)
154
155